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oz6812 04/25/00 oz6812-sf-1.5 page 1 ? copyright 2000 by o 2 micro all rights reserved patent pending acpi cardbus controller features the oz6812 is a pcmcia r2/cardbus controller, providing the most advanced design flexibility for pc cards that interface with advanced notebook designs. ? acpi-pci bus power management interface specification rev 1.1 compliant ? supports onnow lan wakeup, onnow ring indicate, pci clkrun#, pme#, and cardbus cclkrun# ? compliant with pci specification v2.2, 1998 pc card standard 7.0 ? yenta? pci to pcmcia cardbus bridge register compatible ? exca (exchangeable card architecture) compatible registers mappable in memory and i/o space ? intel tm 82365sl pcic register compatible ? supports pcmcia_ata specification ? supports 5v/3.3v pc cards and 3.3v cardbus cards ? supports single pc card or cardbus slot with hot insertion and removal ? supports multiple fifos for pci/cardbus data transfer ? supports direct memory access for pc/pci and pci/way on pc card socket ? programmable interrupt protocol: pci, pci+isa, pci/way, or pc/pci interrupt signaling modes ? win?98 irq and pc-98/99 compliant ? parallel or serial interface for socket power control devices including micrel and ti ? zoomed video support ? integrated pc 98/99 -subsystem vendor id support, with auto lock bit ? led activity pins ordering information oz6812t - 144pin lqfp OZ6812B - 144pin mini-bga general description the oz6812 is an acpi and pc98/99 logo certified, high performance, single slot pc card controller with a synchronous 32-bit bus master/target pci interface. this pc card to pci bridge host controller is compliant with the 1998 pc card standard. this standard incorporates the new 32-bit cardbus while retaining the 16-bit pc card specification as defined by pcmcia release 2.1. cardbus is intended to support ?temporal? add-in functions on pc cards, such as memory cards, network interfaces, fax/modems and other wireless communication cards, etc. the high performance and capability of the cardbus interface will enable the development of many new functions and applications. the oz6812 cardbus controller is compliant with the latest acpi-pci bus power management interface specification. it supports all four power states and the pme# function for maximum power savings and acpi compliance. the device also provides a power-down mode to allow host software to reduce power consumption further by stopping internal clock distribution as well as the pc card socket clock. in addition, an advanced cmos process is utilized to minimize system power consumption. the oz6812 single pcmcia socket supports 3.3v/5v 8/16- bit pc card r2 card or 32-bit cardbus r3 card. the r2 card support is compatible with the intel 82365sl pcic controller, and the r3 card support is fully compliant with the 1998 pc card standard cardbus specification. the oz6812 is a stand alone device, which means that it does not require an additional buffer chip for the pc card socket interface. in addition, the oz6812 supports dynamic pc card hot insertion and removal, with auto configuration capabilities. the oz6812 is fully compliant with the 33mhz pci bus specification, v2.2. it supports a master device with internal cardbus direct data transfer. the oz6812 implements a fifo data buffer architecture between the pci bus and cardbus socket interface to enhance data transfers to cardbus devices. the bi-directional fifo buffer (composed of 16 double words) permits the oz6812 to accept data from a target bus (pci or cardbus interface) while simultaneously transferring data. this architecture not only speeds up data transfers but also prevents system deadlocks.
oz6812 oz6812-sf-1.5 page 2 functional block diagram pci interface pci configuration/ function control registers pci configuration/ function control registers pci arbite r pci arbiter cardbu s fifo data buffering cardbus fifo data buffering power switch contro l power switch control interrup t subsyste m interrupt subsystem 16- bit pc card machin e 8/16-bit pccard machine pc card machin e an d arbite r cardbus pccard machine and arbiter pc card interface single pc card interface powe r switc h interfac e power switch interface acpi/ onnow power management
oz6812 oz6812-sf-1.5 page 3 pin diagram - 144 pin lqfp a10 / cad9 gnt# a16 / cclk a14 / cperr# we# / cgnt# gnd socket_vcc core_vcc ce1# / ccbe0# d7 / cad7 d11 / cad2 ad31 a11 / cad12 oe# / cad11 o 2 micro, inc. oz6812 req# ad30 ad29 gnd ad28 ad27 ad26 ad25 ad24 c/be3# idsel core_vcc ad23 ad22 ad21 pci_vcc ad20 rst# pci_clk gnd ad17 ad16 c/be2# frame# irdy# pci_vcc trdy# devsel# stop# perr# serr# par 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 vccd1# / sclk 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 c/be1# ad15 ad14 ad13 ad12 gnd ad11 pci_vcc ad10 ad9 ad8 c/be0# ad7 pci_vcc ad6 ad5 ad4 ad3 ad2 ad1 ad0 gnd ri_out / pme# mf0 mf1 spkr_out# a u x _ v c c mf3 mf2 core_vcc mf4 mf5 mf6 suspend# vppd0 / slatch vppd1 1 4 4 1 4 3 1 4 2 1 4 1 1 4 0 1 3 9 1 3 8 1 3 7 1 3 6 1 3 5 1 3 4 1 3 3 1 3 2 1 3 1 1 3 0 1 2 9 1 2 8 1 2 7 1 2 6 1 2 5 1 2 4 1 2 3 1 2 2 1 2 1 1 2 0 1 1 9 1 1 8 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 1 2 1 1 1 1 1 0 d9 / cad30 d8 / cad28 d0 / cad27 gnd reg# / ccbe3# a4 / cad22 vs2 / cvs2 a 2 5 / c a d 1 9 a24 / cad17 a12 / ccbe2# a21 / cdevsel# a20 / cstop# a19 / cblock# core_vcc a13 / cpar a18 / rfu a8 / ccbe1# a17 / cad16 a9 / cad14 iow# / cad15 iord# / cad13 ce2# / cad10 d15 / cad8 d14 / rfu d6 / cad5 d13 / cad6 d5 / cad3 d12 / cad4 d4 / cad1 gnd d3 / cad0 cd1/ ccd1# vccd0# / sdata 1 0 9 a2 / cad24 a 7 / c a d 1 8 bvd1/stschg#/ri# / cstschg d10 / cad31 d2 / rfu d1 / cad29 core_vcc cd2 / ccd2# wp/iois16 / cclkrun# bvd2/spkr#/led / caudio w a i t # / c s e r r # rdy/ireq# / cint# vs1 / cvs1 a 0 / c a d 2 6 a1 / cad25 socket_vcc a3 / cad23 inpack# / creq# core_vcc a5 / cad21 reset / crst# a6 / cad20 gnd a23 / cframe# a15 / cirdy# a22 / ctrdy# ad19 ad18
oz6812 oz6812-sf-1.5 page 4 pin list bold text = normal default pin name pci bus interface pins pin number pin name description lqfp bga input type power rail drive ad[31:0] pci bus address input / data: these pins connect to pci bus signals ad[31:0]. a bus transaction consists of an address phase followed by one or more data phases. 3-5, 7-11, 15- 17, 19, 23-26, 38-41, 43, 45- 47, 49, 51-57 d4, b1, c2-1, d2, e4, d1, e3, f3, f1, f2, g1, h2-3, j1, h4, m2, k4, n2, m3, n3, k5, n4, l5, n5, l6, n6, m6, l7, n7, m7, k7 ttl i/o pci_vcc pci spec c/be[3:0]# pci bus command / byte enable: the command signaling and byte enables are multiplexed on the same pins. during the address phase of a transaction, c/be[3:0]# are interpreted as the bus commands. during the data phase, c/be[3:0]# are interpreted as byte enables. the byte enables are to be valid for the entirety of each data phase, and they indicate which bytes in the 32-bit data path are to carry meaningful data for the current data phase. 12, 27, 37, 48 e2, j2, n1, m5 ttl i/o pci_vcc pci spec frame# cycle frame: this input indicates to the oz6812 that a bus transaction is beginning. while frame# is asserted, data transfers continue. when frame# is de-asserted, the transaction is in its final phase. 28 k1 ttl i/o pci_vcc pci spec irdy# initiator ready: this input indicates the initiating agent ? s ability to complete the current data phase of the transaction. irdy# is used in conjunction with trdy#. 29 j3 ttl i/o pci_vcc pci spec trdy# target ready: this output indicates target agent's the oz6812 ? s ability to complete the current data phase of the transaction. trdy# is used in conjunction with irdy#. 31 l1 ttl i/o pci_vcc pci spec stop# stop: this output indicates the current target is requesting the master to stop the current transaction. 33 k3 ttl i/o pci_vcc pci spec idsel initialization device select: this input is used as a chip select during configuration read and write transactions. this is a point-to-point signal. idsel can be used as a chip select during configuration read and write transactions. 13 e1 ttl i pci_vcc pci spec devsel# device select: this output is driven active low when the pci address is recognized as supported, thereby acting as the target for the current pci cycle. the target must respond before timeout occurs or the cycle will terminate. 32 j4 ttl i/o pci_vcc pci spec perr# parity error: the output is driven active low when a data parity error is detected during a write phase. 34 m1 - to pci_vcc pci spec serr# system error: this output is driven active low to indicate an address parity error. 35 l2 - to pci_vcc pci spec
oz6812 oz6812-sf-1.5 page 5 pin number pin name description lqfp bga input type power rail drive par parity: this pin generates pci parity and ensures even parity across ad[31:0] and c/be[3:0]#. during the address phase, par is valid after one clock. with data phases, par is stable one clock after a write or read transaction. 36 l3 ttl i/o pci_vcc pci spec pci_clk pci clock: this input provides timing for all transactions on the pci bus to and from the oz6812. all pci bus signals, except rst#, are sampled and driven on the rising edge of pci_clk. this input can be operated at frequencies from 0 to 33 mhz. 21 g4 - i pci_vcc - rst# device reset: this input is used to initialize all registers and internal logic to their reset states and place most oz6812 pins in a high- impedance state. 20 g2 - i aux_vcc - gnt# grant : this signal indicates that access to the bus has been granted. 2 b2 ttl i pci_vcc pci spec req# request : this signal indicates to the arbiter that the oz6812 requests use of the bus. 1 a1 - to pci_vcc pci spec power control and general interface pins pin number pin name description lqfp bga input type power rail drive ri_out/ pme# ring indicate out: this pin is ring indicate when the following occurs while o 2 mode control b register (index 2eh) bit 7 is set to 1: 1) power control (index+02h) bit 7 set to 1 2) interrupt and general control (index+03h) bit 7 set to 1 3) pci o2micro control 2 (offset: d4h) bit x = 0 power management event: a power management event is the process by which the oz6812 can request a change of its power consumption state. usually, a pme occurs during a request to change from a power saving state to the fully operational state. 59 m8 - to aux_vcc 4ma spkr_out# speaker output: this output can be used to support pc card audio output. see o2 mode e register (index + 3eh), bit 1. 62 k8 ttl i/o aux_vcc 12ma mf[6:0] multifunction terminal [6:0]: see pci multifunction mux register (offset:08h). 69-67, 65-64, 61-60 l10, k9, n11, l9, n10-9, l8 ttl i/o aux_vcc 12ma suspend# suspend: this signal is used to protect the internal registers from clearing when the pci rst# signal is asserted. when low, this signal is used to mask the pci reset during suspend. this pin can be used during suspend to prevent controller reset. 70 n12 ttl i aux_vcc -
oz6812 oz6812-sf-1.5 page 6 pin number pin name description lqfp bga input type power rail drive vppd0/ slatch vppd0: this power input is used with parallel power control chip slatch: this output controls a serial interface power control chip. 71 m11 ttl i/o aux_vcc 12ma vppd1 vppd1: this power input is used a parallel power interface chip. 72 l11 - to aux_vcc 12ma vccd0#/ sdata vccd0#: rail power inputs for use with a parallel power control chip. serial data: this pin serves as output data pin when used with a serial interface of serial power control chip. 73 n13 ttl i/o aux_vcc 12ma vccd1#/ sclk vccd1#: rail power inputs for use with a parallel power control chip. serial clock: the input is used as a reference clock (10-100khz, usually 32khz) to control a serial power control chips. by setting pci o2micro control 2 register (offset:d4h) bit 13 to 1, sclk is an output. default is input mode. 74 m12 ttl i/o aux_vcc 12ma
oz6812 oz6812-sf-1.5 page 7 pc card socket interface pins refer to pci bus interface pin descriptions for details on cardbus function. exceptions: ccd[2:1]#, caudio, cstschg, cvs[2:1] pin number pin name description lqfp bga input type power rail drive reg#/ ccbe3# register access: during pc card memory cycles, this output chooses between attribute and common memory. during i/o cycles for non-dma transfers, this signal is active (low). during ata mode, this signal is always inactive. for dma cycles on the oz6812 to a dma-capable card, reg# becomes dack to the pcmcia card. cardbus command byte enable: in cardbus mode, this pin is the ccbe3#. 125 b8 ttl i/o socket _vcc cardbus spec. a[25:24]/ cad[19, 17] address: pc card socket address 25:24 outputs. cardbus address/data: cardbus mode, these pins are the cad bits 19 and 17. 116, 113 b10, b11 ttl i/o socket _vcc cardbus spec. a23/ cframe# address: pc card socket address 23 output. cardbus frame: in cardbus mode, this pin is the cframe# signal. 111 d10 ttl i/o socket _vcc cardbus spec. a22/ ctrdy# address: pc card socket address 22 output. cardbus target ready: in cardbus mode, this pin is the ctrdy# signal. 109 a13 ttl i/o- pu socket _vcc cardbus spec. a21/ cdevsel# address: pc card socket address 21 output. cardbus device select: in cardbus mode, this pin is the cdevsel# signal. 107 c12 ttl i/o- pu socket _vcc cardbus spec. a20/ cstop# address: pc card socket address 20 output. cardbus stop: in cardbus mode, this pin is the cstop# signal. 105 d11 ttl i/o- pu socket _vcc cardbus spec. a19/ cblock# address: pc card socket address 19 output. cardbus lock: in cardbus mode, this signal is the cblock# signal used for locked transactions. 103 c13 ttl i/o- pu socket _vcc cardbus spec. a18/ rfu address: pc card socket address 18 output. reserved: in cardbus mode, this pin is reserved for future use. 100 d13 ttl to socket _vcc cardbus spec. a17/ cad16 address: pc card socket address 17 output. cardbus address/data: in cardbus mode, this pin is the cad bit 16. 98 f10 ttl i/o socket _vcc cardbus spec. a16/ cclk# address: pc card socket address 16 output. cardbus clock: in cardbus mode, this pin supplies the clock to the inserted card. 108 c11 ttl i/o socket _vcc cardbus spec.
oz6812 oz6812-sf-1.5 page 8 pin number pin name description lqfp bga input type power rail drive a15/ cirdy# address: pc card socket address 15 output. cardbus initiator ready: in cardbus mode, this pin is the cirdy# signal. 110 b12 ttl i/o- pu socket _vcc cardbus spec. a14/ cperr# address: pc card socket address 14 output. cardbus parity error: cardbus mode, this pin is the cperr# signal. 104 e10 ttl i/o- pu socket _vcc cardbus spec. a13/ cpar address: pc card socket address 13 output. cardbus parity: in cardbus mode, this pin is the cpar signal. 101 e11 ttl i/o socket _vcc cardbus spec. a12/ ccbe2# address: pc card socket address 12 output. cardbus command/byte enable: in cardbus mode, this pin is the ccbe2# signal. 112 a12 ttl i/o socket _vcc cardbus spec. a[11:9]/ cad [12,9,14] address: pc card socket address 11:9 output. cardbus address/data: in cardbus mode, these pins are the cad bits 12, 9 and 14. 95, 89, 97 f12, h12, e13 ttl i/o socket _vcc cardbus spec. a8/ ccbe1# address: pc card socket address 8 output. cardbus command/byte enable: in cardbus mode, this pin is the ccbe1# signal. 99 e12 ttl i/o socket _vcc cardbus spec. a[7:0]/ cad[18] [20:26] address: pc card socket address 7:0 outputs. cardbus address/data: in cardbus mode, these pins are the cad bits 18 and 20:26. 115, 118, 120, 121, 124, 127, 128, 129 a11-10, b9, a9-7, b7, d7 ttl i/o socket _vcc cardbus spec. d15/ cad8 data: pc card socket i/o data bit 15. cardbus address/data: in cardbus mode, this pin is the cad bit 8. 87 h11 ttl i/o socket _vcc cardbus spec. d14/ rfu data: pc card socket i/o data bit 14. reserved: in cardbus mode, this pin is reserved for future use. 84 j12 ttl i/o socket _vcc cardbus spec. d[13:3]/ cad[6, 4, 2, 31, 30, 28, 7, 5, 3, 1, 0] data: pc card socket i/o data bits 13:3. cardbus address/data: in cardbus mode, this pin is the cad bit 6 4, 2, 31, 30, 28, 7, 5, 3, 1, and 0, respectively. 82, 80, 77, 144, 142, 140, 85, 83, 81, 79, 76 k13-12, l12, c3, a2, d5, j13, j11, j10, l13, m13 ttl i/o socket _vcc cardbus spec. d2/ rfu data: pc card socket i/o data bit 2. reserved: in cardbus mode, this pin is reserved for future use. 143 b3 ttl i/o socket _vcc cardbus spec. d[1:0]/ cad[29,27] data: pc card socket i/o data bits 1:0. cardbus address/data: in cardbus mode, these pins are the cad bits 29 and 27, respectively. 141, 139 c4, a3 ttl i/o socket _vcc cardbus spec. oe#/ cad11 output enable : this output goes active (low) to indicate a memory read from the oz6812 to pc card. cardbus address/data: in cardbus mode, this pin is the cad bit 11. 92 g12 ttl i/o socket _vcc cardbus spec. we#/ cgnt# write enable : this output goes active (low) to indicate a memory write from the oz6812 to the pc card socket. cardbus grant: in cardbus mode, this pin is the cgnt# signal. 106 b13 ttl to socket _vcc cardbus spec.
oz6812 oz6812-sf-1.5 page 9 pin number pin name description lqfp bga input type power rail drive iord#/ cad13 i/o read : this output goes active (low) for i/o reads from the oz6812 to the socket. cardbus address/data: in cardbus mode, this pin is the cad bit 13. 93 g10 ttl i/o socket _vcc cardbus spec. iow#/ cad15 i/o write : this output goes active (low) for i/o writes from the oz6812 to the socket. cardbus address/data: in cardbus mode, this pin is the cad bit 15. 96 f11 ttl i/o socket _vcc cardbus spec. wp/ iois16#/ cclkrun# write protect / i/o is 16-bit: in memory mode, this input is indicates the status of the write protect switch on the pc card. in i/o mode, this input indicates the size of current data transfer on the pc card. cardbus clock run: in cardbus mode, this pin is the cclkrun# signal, which starts and stops the cardbus cclk. to enable the clkrun# signal, exca register 3bh bit[3:2] must be enabled. 136 a4 ttl i/o-pu socket _vcc cardbus spec. inpack#/ creq# input acknowledge: the inpack# function is not applicable in pci bus environments. this pin is provided for legacy card compatibility. cardbus request: in cardbus mode, this pin is the creq# signal. 123 c8 - i-pu socket _vcc cardbus spec. rdy/ireq#/ cint# ready / interrupt request: in memory mode, this input indicates that the card is ready or busy. in i/o mode, this input indicates a card interrupt request. cardbus interrupt: in cardbus mode, this pin is the cint# signal. this signal is active-low and level-sensitive. 132 c6 - i-pu socket _vcc cardbus spec. wait#/ cserr# wait: this pin is driven by the pc card to delay completion of the current cycle. cardbus system error: in cardbus mode, this pin is the cserr# signal. 133 a5 ttl i-pu socket _vcc cardbus spec. cd[2:1]/ ccd[2:1]# card detect : these inputs indicate a card is present in the socket. they are internally pulled high to aux_vcc. cardbus card detect: in cardbus mode, these inputs are used with cvs[2:1] to detect presence and type of card. 137, 75 c5, k10 ttl i-pu- schmitt aux_vcc cardbus spec. ce2#/ cad10 card enable 2: this pin is driven low to control byte/word card access. ce2# enables odd- numbered address bytes. cardbus address/data: in cardbus mode, this pin is the cad bit 10. 91 g13 ttl i/o socket _vcc cardbus spec. ce1#/ ccbe0# card enable 1: this pin is driven low to control byte/word card access. ce1# enables even- numbered address bytes. when configured for 8- bit cards, ce1# is active and a0 is used to indicate access of odd- or even-numbered bytes. cardbus command/byte enable: in cardbus mode, this pin is the ccbeo# signal. 88 h13 ttl i/o socket _vcc cardbus spec.
oz6812 oz6812-sf-1.5 page 10 pin number pin name description lqfp bga input type power rail drive reset/ crst# reset: this active high output resets the card. to prevent reset glitches, this signal is high- impedance unless a card is seated in the socket, card power is applied, and the card ? s interface signals are enabled. cardbus reset: in cardbus mode, this pin is the crst# output. 119 c9 ttl to socket _vcc cardbus spec. bvd2/spkr#/ led / caudio battery voltage detect 2 / speaker / led: in memory mode, this input serves as the bvd2 (battery warning status) input. in i/o mode, this input can be configured as the card ? s spkr# audio input or drive-active led input. cardbus audio: in cardbus mode, this pin is the caudio input. 134 d6 - i-pu socket _vcc - bvd1/ stschg#/ri#/ cstschg battery voltage detect 1 / status change / ring indicate: in memory mode, this is the bvd1 (battery-dead status) input. in i/o mode, this is the stschg# input indicating that the card ? s internal status has changed, or the ring indicates input for wakeup-on-ring system power management support. see bit 7 of the interrupt and general contro l register (03h). cardbus status change: in cardbus mode, this pin is the cstschg. this pin can be used to generate pme#. 135 b5 - i-pu socket _vcc - vs[2:1]/ cvs[2:1] voltage sense: these pins are used in conjunction with cd[2:1] to determine the type and voltage of a card. these pins are internally pulled high to aux_vcc. see table 1. cardbus voltage sense: in cardbus mode, these pins are the cvs[2:1] pins. 117, 131 d9, b6 ttl i/o-pu aux_vcc cardbus spec. socket_vcc socket power: these pins are the power rail input for the socket interface control logic. these pins can be 0, 3.3, or 5 v,. the socket interface outputs will operate at the voltage applied to these pins. 90, 126 g11, c7 - pwr - -
oz6812 oz6812-sf-1.5 page 11 power, ground, and reserved pins pin number pin name description lqfp bga input type power rail drive aux_vcc auxiliary vcc : this pin is connected to the system ? s 3.3/5v power supply. for the device to 5v tolerant, connect to +5v power. 63 m9 - pwr - - core_vcc core_vcc: this pin provides power to the core circuitry of the oz6812. it must be connected to a 3.3v power supply. 14, 66, 86, 102, 122, 138 f4, m10, h10, d12, d8, b4 - pwr - - pci_vcc pci bus vcc: these pins can be connected to either a 3.3v or5v power supply. the pci bus interface will operate at the voltage applied to these pins, independent of the voltage applied to other oz6812 pin groups. 18, 30, 44, 50 g3, k2, m4, k6 - pwr - - gnd system ground 6, 22, 42, 58, 78, 94, 114, 130 d3, h1, l4, n8, k11, f13, c10, a6 - gnd - - legend i/o type description power rail source of output?s power i input pin 1 aux_vcc: outputs powered from aux_vcc i-pu input pin with internal pull-up 2 socket_vcc: outputs powered from the socket i-pu schmitt input pin with internal pull-up and schmitt trigger o output 3 pci_vcc: outputs powered from pci bus power supply od open-drain 4 core_vcc: outputs powered from the core_vcc to tri-state output to-pu tri-state output with internal pull-up od-pu open-drain output with internal pull-up pwr power pin
oz6812 oz6812-sf-1.5 page 12 package information - 144 pin lqfp he e hd d a 2 a 1 y m 0.08(0.003) gage plane eb l 1 c 0.25 l symbol millimeter inch min. nom. max. min. nom. max. a1 a2 b c d e e hd he l l1 y 0.05 0.10 0.15 0.002 0.004 0.006 0.090 0.200 0.004 0.008 20.00 0.787 0.50 0.020 22.00 0.866 0.45 0.60 0.75 0.018 0.024 0.030 1.00 0.039 0.08 0.003 0707 20.00 0.787 22.00 0.866 0.17 0.22 0.27 0.007 0.009 0.011 1.35 1.40 1.45 0.053 0.055 0.057
oz6812 oz6812-sf-1.5 page 13 144 pin mini - bga 7. solder ball depopulation is allowed. depopulation is the omission of 3. "n" represents the maximum number of solder balls for matrix size 4. dimension "b" is measured at the maximum solder ball diameter after 5. primary datum z and seating plane are defined by the spherical 6. a1 corner must be identified by ink mark, metallized markings, identation or other feature of package body, lid or integral balls from a full matrix (m1 or m2). 1. dimensioning and tolerancing per asme y14.5m-1994. 2. "e" represents the solder ball grid pitch. m1 and m2. crowns of the solder balls. heatslug, on the top surface of the package. reflow and parallel to primary datum z, the original solder ball notes: 8. ball pad a1 corner indicator (nc) solder ball diameter is 0.45 mm.

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